1. Field of the Invention
The present invention relates to a semiconductor memory device constituted by a dynamic random access memory (DRAM) which has a trench capacitor and a side-wall contact, and a method of fabricating the same.
2. Description of the Related Art
The technique disclosed in Jpn. Pat. Appln. KOKOKU Publication No. 3-69185 will be described with reference to FIGS. 1 and 2. FIG. 1 is a plan view of a pattern showing the trench capacitor cell portion of a conventional DRAM, and FIGS. 2A and 2B are cross-sectional views respectively along the lines 2A--2A and 2B--2B in FIG. 1.
A trench 202 is formed on a P type silicon substrate 201, with an insulating film 203 formed on the inner wall of the trench 202. Phosphorus-doped polycrystalline silicon 204 is buried in the trench 202, and an oxide film 206 is formed on the polycrystalline silicon. To remove a part of the insulating film 203 at the upper edge portion of the trench 202, a resist film is formed on the trench 202 and an opening (215) is made. As a result, a window 205 is formed through which phosphorus from the polycrystalline silicon 204 is diffused into the substrate, thus forming an N type diffusion layer 207. Formed on the substrate are gate insulating films 208a and 208b, gate electrodes 209a and 209b (word lines), and source/drain diffusion layers 210a and 210b. The N type diffusion layer 207 is connected to the source/drain diffusion layer 210a. Reference numeral "211" denotes a bit line contact.
The above structure has the following shortcomings. First, the region which includes the inner wall of the trench 202, the N type diffusion layer 207 and the substrate 201 has a gate control diode structure. If a potential is given to the polycrystalline silicon 204, a depletion layer stretches around the insulating film 203 on the trench's inner wall and an inversion layer is continuously formed along the outer surface of the trench 202, starting from the N type diffusion layer 207. This increases the junction leak current between the substrate 201 and the N type diffusion layer 207, which contacts the polycrystalline silicon 204.
To avoid the junction leak current, the capacitance of the capacitor should be reduced by some amount. This is accomplished by forming the insulating film 203 thick on the trench's inner wall at the price of an increase in capacitance.
Secondly, punch-through may occur in the N type diffusion layer 207 around the upper portion of the trench 202 because of the short distance from another source/drain region 210b. While this problem can be overcome by making the distance sufficient enough not to cause punch-through, this approach stands in the way of higher integration.
Thirdly, according to the above structure, the gate electrode 209b of another adjoining cell transistor is formed on the oxide film 206, which electrically isolates the gate electrode 209b from the polycrystalline silicon 204. The oxide film 206 has a thickness of several thousand angstroms, and stress is applied to the substrate in this oxidizing step, yielding crystal defects 216 around the upper portion of the trench 202.
The crystal defects 216, if formed, accelerate the problem of the junction leak current. The oxide film 206 should therefore be made thin enough not to produce the crystal defects. It is however difficult to make the oxide film 206 thinner than the current thickness in view of the insulation breakdown of the polycrystalline silicon film 204.
In short, according to the prior art, the potential applied to the polycrystalline silicon filling the trench may cause punch-through to the source/drain regions of another adjoining cell or may generate the junction leak current between the diffusion layer contacting the polycrystalline silicon and the substrate. In particular, this junction leak current becomes more prominent by the crystal defects (216) formed around the upper portion of the trench. The crystal defects are an inevitable result of forming the oxide film which accomplishes insulative isolation from another gate electrode (polycrystalline silicon) on the trench.